With the reduction of the critical dimensions of integrated circuits and, more particularly, the width of the gate of MIS transistors, it has proved necessary to modify the construction processes for the sources and drains of said transistors.
Thus, the smaller the gate width, the greater the lateral diffusion of the source-drain implantation beneath the gate becomes, so that it is more disadvantageous. In addition, the MIS transistor may become more sensitive to the puncturing phenomenon between the source and the drain corresponding to the leakage current between the source and the drain for a zero gate voltage. Finally, the reduction of said gate width leads to a premature ageing of the MIS transistor through the injection of hot carriers into the gate insulant. This phenomenon becomes more prejudicial as the concentration of the dopants at the edges of the transistor gate becomes high.
For all these reasons, type n and also type p transistors are now produced by a double implantation process, referred to as the low doped drain or LDD process and which solves the aforementioned problems for technologies in which the gate width is typically below 2 micrometers. This process becomes absolutely indispensable in submicron technologies.
This overall process is more particularly described in the IBM EP-A-0 054 117. It essentially consists of forming the gate of the transistors in a polycrystalline silicon film, thermally oxidizing the substrate and the gate of the transistors, carrying out a first low dose implantation, forming spacers on either side of the transistor gate and then carrying out a second high dose implantation in order to form the double junction sources and drains of the transistors.
The first low does implantation makes it possible to considerably reduce the dopant concentration perpendicular to the gate of the transistors and therefore partly solve the aforementioned electrical problems. The second high dose implantation is necessary for fulfilling the function of the source and drain of the transistors, because the resistance of the junctions obtained by the low dose implantation is too high.
In order to ensure that said high dose implantation is not superimposed on the low dose implantation zone, it is necessary to move it physically away from the edge of the gate. This is brought about by carrying out the second implantation through spacers or spacing strips. These spacing strips are obtained by the isotropic deposition of an insulating film on the complete structure, followed by the full plate etching of said insulating film in order to form the spacers on the gate edges.
During the production of the spacers, there is generally a large consumption (several dozen nm) of the field insulant (generally field oxide) used for the electrical insulation of the transistors. This field insulant consumption modifies its electrical properties, which can favor the formation of parasitic transistors in said insulations.
Moreover, the aforementioned IBM process does not make it possible to obtain MIS integrated circuits operating with a high supply voltage. Moreover, the transistors obtained have a low transconductance. The term high supply voltage is understood to mean voltages of 8 V for transistor gate widths of 500 nm, a voltage of 5 V for gate widths of 300 nm and a voltage of 3 V for gate widths below 200 nm.
In order to obviate these disadvantages, R. IZAWA et al proposed a modification to the IBM process described in the IEDM article 87, pp 38-41 "The impact of gate-drain overlapped LDDD (GOLD) for deep submicron VLSI'S". In this process, successive formation takes place on the thermal oxidant of the substrate of a first polycrystalline silicon coating, a second thermal oxide and a second polycrystalline silicon coating. This is followed by the etching through an insulating mask of said second polycrystalline silicon coating and then the first low dose implantation into the substrate through the second thermal oxidation coating, the first polycrystalline silicon coating and the first thermal oxidation coating. Following the low dose implantation, spacers are formed by the deposition of a second oxide coating on the complete structure and then the full plate etching of said oxide coating.
By using the spacers as a mask, an etching takes place of the first polycrystalline silicon coating, followed by an oxidation of the etched edges of said first silicon coating. Only then does the high dose second implantation take place.
The use of a first polycrystalline silicon coating permits an overlap of the transistor gate over the weakly implanted source and drain areas, thus reducing the electrical resistance of said low implantation areas. Moreover, this process makes it possible to increase the transconductance of the transistors, as well as the current in their channel.
Unfortunately, the transistors obtained have an inadequate resistance to puncturing between the source and the drain, thus limiting the supply voltage applied to said transistors. The limited puncturing resistance of "GOLD" transistors is due to the fact that n+pn+ or p+np+ transistors are buried beneath the channel of the, respectively, n-pn- and p-np- transistors.
In addition, this process suffers from performance difficulties. More particularly, the etching of the second polycrystalline silicon coating requires a selectivity higher than 100 relative to the second silicon oxide coating, bearing in mind the limited oxide coating thickness necessary for avoiding the obtaining of a floating gate, which is difficult to carry out with the etching procedures used.